The present disclosure relates to sense circuits for semiconductor devices. More particularly, the disclosure relates to semiconductor devices that incorporate a voltage compensation device to center a band of ‘high’ and ‘low’ eDRAM bitline signals around the switch point of a single-ended sense amplifier.
In conventional dynamic random-access memory (DRAM), the sense signal from a memory cell is generated by charge sharing the charge stored in the memory cell with a precharged bitline, and then the developed sense signal on the precharged bitline is compared to a reference bitline.
DRAM arrays generate bitline voltages which must be interpreted as being ‘high’ or ‘low’ to discern between a ‘1’ or ‘0’ digital state. Traditional differential sense schemes use a reference voltage level which can be centered between the expected band of ‘0’ data-voltage levels and expected ‘1’ data-voltage levels. Differential sense systems have one input to receive a reference-voltage level and another input to receive a data-voltage signal and an analog comparison is made to distinguish ‘high’ and ‘low’ logic states. The ability to center the reference level between the data levels allows for optimized yield, reliability and allows signal margin testing.
To achieve maximum density, a large number of memory cells are typically connected to a single bitline in order to reduce the area overhead of the local amplifier. However, adding cells to a bitline also increases the bitline capacitance, and consequently reduces the transfer ratio (Ccell/(Cb1+Ccell)), which in turn reduces the developed sense signal. Typically, the number of bits (memory cells) per bitline is chosen to minimize the number of sense amps (overhead) while maintaining enough sense signal to detect the stored state of a memory cell reliably.
The amplitude of the sense signal ΔVb1 from a memory cell is a function of the cell capacitance, the bitline capacitance, the cell voltage and the bitline precharge voltage, as set forth in the following formula:ΔVb1=(Vcell−VBLEQ)*(Ccell/(Cb1+Ccell))                where                    Vcell=voltage stored in the memory cell;            VBLEQ=bitline precharge voltage;            Ccell=cell capacitance; and            Cb1=bitline capacitance.                        
Newer embedded DRAM (eDRAM) arrays use a single-ended sense scheme wherein bitlines are directly coupled to a sensing-inverter having a switch-point voltage. The eDRAM array bitlines are shortened to increase the bitline signal levels and the data-level is sensed as being above or below the inverter switch-point voltage. The sensing-inverter switch-point voltage is a function of NFET and PFET Vt, transconductance, temperature and supply voltage (PVT), and moves largely independent from bitline signal level changes.
Single-ended sense schemes have no means to adjust their voltage switch points as do traditional differential sense schemes using a cross-coupled 2-input sense amplifier for example. The ability to center the switch-point on the midpoint of the ‘0’ and ‘1’ data voltage levels is lost using single-ended sense schemes.
The loss of this centering function makes it difficult to design and test an eDRAM array for high yield, maximum retention, and reliability. True signal margin testing cannot be performed. Efforts to compensate for this loss of signal centering by adjustments in Vdd, or by restrictions in operating temperature limit customer usage and make a design uncompetitive. Tighter manufacturing controls can improve the eDRAM yield but increase manufacturing costs.